Executive Control & Integration Layer
The next evolutionary layer: From reflexes to goal-directed behavior
Overview
The Executive Control Layer represents the transition from basic reflexes and simple commands to sophisticated goal-directed behavior. This layer integrates all existing systems (brainstem, basal ganglia, limbic system) into coordinated, goal-oriented actions.
In biological terms, this moves Chapp-E from "lizard brain" functions (survival, reflexes) and basic mammalian functions (emotion, memory) to the sophisticated primate functions of rational thought, complex planning, and executive decision-making.
Why This Layer is Next
From Reflex to Planning
Your current system has:
- Basic input handling (FSM, GCS)
- Simple command execution (Shell)
- State management (Consciousness)
- Memory functions (Working Memory buffer)
The Executive Control Layer moves beyond immediate reflexes to:
- Conscious planning and decision-making
- Inhibition of impulsive actions
- Complex multi-step task execution
- Goal management and prioritization
Integration of Existing Systems
This layer ties together:
Simple Commands → Complex Sequences → Goal Achievement
FSM (State Management) + Working Memory + Consciousness
→ Executive Planning → Multi-step Execution
Core Subsystems
1. Working Memory Management (Prefrontal Cortex)
Location: neural/networks/executive_control/working_memory_64.asm
Status: ✅ FULLY IMPLEMENTED - Multi-slot working memory with priority management
Implemented Features:
- ✅ Multi-Slot Memory
- 3 independent memory slots (64 bytes each = 192 bytes total)
- Each slot can store different task information
- Automatic slot allocation and deallocation
- ✅ Priority Management
- 4 priority levels: HIGH (3), MEDIUM (2), LOW (1), NONE (0)
- Priority flags stored per slot
- High-priority tasks can preempt low-priority ones
- ✅ State Tracking
- IDLE: No active slots
- ACTIVE: One or more slots in use
- OVERLOADED: All slots full (capacity reached)
- 🟡 Integration with Attention Network
- Planned for future implementation
- Will filter input based on current goals
- Will maintain focus on relevant information
- 🟡 Integration with Salience Network
- Planned for future implementation
- Will detect important stimuli
- Will interrupt current task for high-priority events
Memory Layout (Current Implementation):
| Address | Size | Purpose | Status |
|---|---|---|---|
0x200000 |
1 byte | Working memory state (IDLE=0, ACTIVE=1, OVERLOADED=2) | ✅ Active |
0x200001 |
1 byte | Number of active memory slots (0-3) | ✅ Active |
0x200002 |
64 bytes | Memory slot 0 (current task) | ✅ Active |
0x200042 |
64 bytes | Memory slot 1 (background task) | ✅ Active |
0x200082 |
64 bytes | Memory slot 2 (interrupt handler) | ✅ Active |
0x2000C2 |
3 bytes | Priority flags (1 byte per slot) | ✅ Active |
Total Memory: 194 bytes (0x200000 - 0x2000C2)
API Functions:
; Initialize Working Memory
extern working_memory_init
call working_memory_init
; Get current state (returns in AL: 0=IDLE, 1=ACTIVE, 2=OVERLOADED)
extern working_memory_get_state
call working_memory_get_state
; AL = state
; Allocate a slot
; Input: AL = priority (WM_PRIORITY_HIGH/MEDIUM/LOW)
; RSI = data pointer
; RCX = data length (max 64 bytes)
; Output: AL = slot number (0-2) or 0xFF if no slot available
extern working_memory_allocate_slot
mov al, WM_PRIORITY_HIGH
mov rsi, data_ptr
mov rcx, data_len
call working_memory_allocate_slot
; AL = slot number or 0xFF
; Free a slot
; Input: AL = slot number (0-2)
extern working_memory_free_slot
mov al, slot_number
call working_memory_free_slot
; Get slot data pointer
; Input: AL = slot number (0-2)
; Output: RAX = pointer to slot data (or 0 if invalid)
extern working_memory_get_slot
mov al, slot_number
call working_memory_get_slot
; RAX = pointer to slot data
2. Decision-Making & Planning System
Location: neural/networks/executive_control/planning_64.asm
Status: ✅ FULLY IMPLEMENTED - Multi-step goal planning and execution coordination
Implemented Features:
- ✅ Multi-step Planning
- Break complex goals into up to 8 sub-tasks
- Each step can be up to 32 bytes
- Sequential execution with state tracking
- ✅ Goal Storage
- 64-byte goal buffer
- Goal string storage and retrieval
- Goal validation and parsing
- ✅ State Management
- IDLE: No active plan
- PLANNING: Creating plan from goal
- EXECUTING: Running plan steps
- COMPLETE: All steps finished
- ERROR: Plan execution failed
- ✅ Step Execution
- Get next step in sequence
- Track current step index
- Reset plan for new goals
- 🟡 Goal Evaluation
- Planned for future implementation
- Will evaluate different possible actions
- Will consider past experience (hippocampus integration)
Memory Layout (Current Implementation):
| Address | Size | Purpose | Status |
|---|---|---|---|
0x201000 |
1 byte | Planning state (IDLE=0, PLANNING=1, EXECUTING=2, COMPLETE=3, ERROR=4) | ✅ Active |
0x201001 |
1 byte | Number of steps in current plan (0-8) | ✅ Active |
0x201002 |
1 byte | Current step being executed (0-7) | ✅ Active |
0x201003 |
256 bytes | Plan steps buffer (8 steps × 32 bytes each) | ✅ Active |
0x201100 |
64 bytes | Current goal storage | ✅ Active |
Total Memory: 355 bytes (0x201000 - 0x201163)
API Functions:
; Initialize Planning System
extern planning_init
call planning_init
; Create a plan from a goal
; Input: RSI = goal string pointer
; RCX = goal length
; Output: CF = 1 if plan created, CF = 0 if error
extern planning_create_plan
mov rsi, goal_string
mov rcx, goal_length
call planning_create_plan
; CF = success flag
; Get next step in plan
; Output: RAX = pointer to step data (or 0 if no more steps)
; AL = step number (0-7) or 0xFF if no steps
extern planning_get_next_step
call planning_get_next_step
; RAX = step pointer, AL = step number
; Reset plan (clear all steps and goal)
extern planning_reset
call planning_reset
; Get current state
; Output: AL = state (PLAN_STATE_*)
extern planning_get_state
call planning_get_state
; AL = state
Integration Points:
| System | Integration |
|---|---|
| FSM (Basal Ganglia) | Extended state management for complex tasks |
| Working Memory (PFC) | Store and retrieve planning information |
| Hippocampus | Retrieve past experiences for decision-making |
| Consciousness | Maintain awareness during planning |
| Brain Controller | Route planning messages to execution systems |
3. Error Correction & Reward System
Location: neural/cerebellum/ (Error Correction) + neural/basal_ganglia/substantia_nigra/ (Reward)
Cerebellum: Error Detection & Correction
- Command Error Detection
- Monitor command execution for errors
- Compare expected vs. actual outcomes
- Generate error correction signals
- Motor Coordination
- Fine-tune command execution
- Optimize action sequences
- Learn from execution patterns
Substantia Nigra: Reward System (Dopamine)
- Success Reinforcement
- Reinforce "good" decisions or commands that succeed
- Strengthen neural pathways for successful actions
- Create positive feedback loops
- Learning Mechanism
- Enable learning from experience
- Prioritize actions that lead to success
- Suppress actions that lead to errors
Integration Flow:
Command Execution → Cerebellum (Error Check)
→ Success? → Substantia Nigra (Reward) → Strengthen Pathway
→ Error? → Cerebellum (Correction) → Retry/Adjust
Implementation Architecture
Message Flow for Executive Control
User Input → Brain Controller → Executive Control System
↓
[Goal Evaluation]
↓
[Planning Module] → Working Memory (Store Plan)
↓
[Execution Module] → FSM (State Management)
↓
[Monitoring Module] → Cerebellum (Error Check)
↓
[Reward Module] → Substantia Nigra (Reinforcement)
↓
Output → Brain Controller → I/O System
System IDs (New)
| System ID | System Name | Brain Region |
|---|---|---|
0x07 |
Executive Control | Prefrontal Cortex |
0x08 |
Cerebellum | Cerebellum |
0x09 |
Reward System | Substantia Nigra |
0x0A |
Attention Network | Attention Network |
0x0B |
Salience Network | Salience Network |
New Message Types
| Message Type | Value | Description |
|---|---|---|
MSG_TYPE_GOAL |
0x60 |
Goal definition message |
MSG_TYPE_PLAN |
0x70 |
Execution plan message |
MSG_TYPE_ERROR |
0x80 |
Error detection message |
MSG_TYPE_REWARD |
0x90 |
Reward/reinforcement message |
Directory Structure for Executive Control
neural/
├── networks/
│ ├── executive_control/ → Main executive control system
│ │ ├── planning.asm → Multi-step planning logic
│ │ ├── decision_making.asm → Decision evaluation
│ │ ├── goal_management.asm → Goal tracking and prioritization
│ │ └── execution_coordinator.asm → Coordinates execution
│ │
│ ├── attention/ → Attention network
│ │ ├── focus_manager.asm → Maintains focus on current task
│ │ └── filter.asm → Filters irrelevant input
│ │
│ └── salience/ → Salience network
│ ├── importance_detector.asm → Detects important events
│ └── interrupt_handler.asm → Handles high-priority interrupts
│
├── cerebellum/ → Error correction
│ ├── error_detector.asm → Detects execution errors
│ ├── correction_engine.asm → Generates corrections
│ └── motor_coordinator.asm → Fine-tunes execution
│
├── basal_ganglia/
│ └── substantia_nigra/ → Reward system
│ ├── reward_calculator.asm → Calculates reward values
│ ├── pathway_strengthener.asm → Strengthens successful pathways
│ └── learning_engine.asm → Enables learning from experience
│
└── cerebrum/
└── cortex/
└── frontal/
└── prefrontal/
└── informationintegration/
├── decisionmaking/ → Decision-making logic
├── planning/ → Planning algorithms
├── problemsolving/ → Problem-solving strategies
└── shorttermworkingmemory/ → Enhanced working memory
├── buffer.asm → (Existing - to be enhanced)
├── priority_manager.asm → New: Priority management
└── slot_manager.asm → New: Multi-slot management
Implementation History & Debugging
The Great Memory Conflict (2024)
The implementation of the Executive Control layer revealed a critical memory mapping issue that required extensive debugging and system redesign.
Initial Implementation
Both systems were initially placed near the kernel:
- Working Memory:
0x100200-0x1002C2 - Planning System:
0x100300-0x100463
This caused immediate system crashes during GRUB kernel loading, before any debug messages could appear.
The Investigation Process
Through systematic binary search debugging, we discovered:
- 45-byte boundary: Only 45 bytes were writable from
0x100202 - 46-byte crash: Writing the 46th byte caused immediate system crash
- Invalid region:
0x100242(WM_SLOT_1) was completely invalid - Root cause: Memory addresses too close to kernel code region at
0x100000
Debugging Methodology
We used incremental testing to isolate the problem:
- Started with minimal function (just
ret) - ✅ worked - Added state byte writes - ✅ worked
- Added memory clearing with
rep stosb- ❌ crashed - Replaced with manual loops - ❌ still crashed
- Tested single-byte writes - ✅ worked
- Binary search for boundary: 8, 32, 40, 44, 45 bytes ✅ | 46, 48, 64 bytes ❌
- Identified exact boundary at 46 bytes from
0x100202
The Solution
We moved all system data structures to 0x200000 (2MB) or higher:
- Working Memory:
0x100200→0x200000(2MB) - Planning System:
0x100300/0x100400→0x201000(2MB + 4KB)
This provides a full 1MB buffer between the kernel and system data, ensuring complete safety.
Current Status
✅ Both systems are now fully functional and tested:
- ✅ Working Memory initializes successfully
- ✅ Planning System initializes successfully
- ✅ Both systems integrated into Brain Controller
- ✅ System boots without crashes
- ✅ All memory addresses verified and documented
Implementation Phases
Phase 1: Enhanced Working Memory ✅ COMPLETE
- ✅ Multi-slot memory system (3 slots × 64 bytes)
- ✅ Priority management (HIGH, MEDIUM, LOW, NONE)
- ✅ State tracking (IDLE, ACTIVE, OVERLOADED)
- ✅ Slot allocation and deallocation
- ✅ Memory address migration to safe region (0x200000)
- 🟡 Integration with Attention network (planned)
Phase 2: Basic Planning System ✅ COMPLETE
- ✅ Goal definition and storage (64 bytes)
- ✅ Multi-step planning (up to 8 steps × 32 bytes)
- ✅ State management (IDLE, PLANNING, EXECUTING, COMPLETE, ERROR)
- ✅ Step execution and tracking
- ✅ Memory address migration to safe region (0x201000)
- 🟡 Integration with FSM for state management (planned)
Phase 3: Error Correction
- Implement Cerebellum error detection
- Add correction feedback to execution
- Integrate with Brain Controller message system
- Test error recovery scenarios
Phase 4: Reward System
- Implement Substantia Nigra reward calculation
- Add pathway strengthening mechanism
- Create learning from experience
- Test reinforcement of successful actions
Phase 5: Full Integration
- Integrate all subsystems
- Implement Attention and Salience networks
- Full multi-step goal execution
- End-to-end testing
Example: Multi-step Command Execution
With Executive Control, a command like "compile and run program" would:
- Goal Definition: Executive Control receives "compile and run program"
- Planning: Breaks into steps:
- Step 1: Compile source code
- Step 2: Check for errors
- Step 3: If no errors, run program
- Step 4: If errors, report and stop
- Execution: FSM manages state transitions for each step
- Monitoring: Cerebellum checks each step for errors
- Adaptation: If error detected, adjust plan or retry
- Reward: If successful, strengthen this pathway for future
Integration with Brain Controller
The Executive Control layer is fully integrated into the Brain Controller message system:
Initialization Sequence
braincontroller_init:
; ... other initializations ...
; Initialize Executive Control systems
extern working_memory_init
call working_memory_init
extern planning_init
call planning_init
; ... continue initialization ...
System IDs
Executive Control uses System ID 0x07 for message routing:
SYS_ID_EXEC equ 0x07 ; Executive Control (Prefrontal Cortex)
Message Types
New message types for Executive Control:
| Message Type | Value | Description | Status |
|---|---|---|---|
MSG_TYPE_GOAL |
0x60 |
Goal definition message | ✅ Defined |
MSG_TYPE_PLAN |
0x70 |
Execution plan message | ✅ Defined |
MSG_TYPE_ERROR |
0x80 |
Error detection message | 🟡 Planned |
MSG_TYPE_REWARD |
0x90 |
Reward/reinforcement message | 🟡 Planned |
File Structure
The Executive Control layer is implemented in:
neural/networks/executive_control/
├── working_memory_64.asm ✅ Complete - Multi-slot working memory
└── planning_64.asm ✅ Complete - Multi-step planning system
Build Integration
Both modules are compiled and linked in scripts/build_multiboot.ps1:
# Assemble Executive Control modules
nasm -f elf64 neural/networks/executive_control/working_memory_64.asm -o build/working_memory_64.o
nasm -f elf64 neural/networks/executive_control/planning_64.asm -o build/planning_64.o
# Link with other modules
ld ... build/working_memory_64.o build/planning_64.o ...
Biological Inspiration
This layer is inspired by:
- Prefrontal Cortex: Executive functions, working memory, planning ✅ Implemented
- Cerebellum: Error correction, motor coordination, learning 🟡 Planned
- Substantia Nigra: Dopamine reward system, pathway strengthening 🟡 Planned
- Attention Network: Focus and filtering of information 🟡 Planned
- Salience Network: Detection of important events 🟡 Planned
Integration with Neuromodulator System
The Executive Control layer is designed to be influenced by the Neuromodulator System, creating dynamic, adaptive behavior:
Chemical Effects on Executive Control
| Chemical | Effect on Working Memory | Effect on Planning |
|---|---|---|
| High Dopamine | More exploration, bolder slot allocation | More ambitious goals, longer plans |
| High Serotonin | Better impulse control, careful slot management | More conservative, careful planning |
| High Acetylcholine | Better focus, clearer memory retention | More focused, step-by-step execution |
| High Cortisol | Reduced capacity, risk of overload | Risk-averse, shorter-term planning |
Regional Modulation
Executive Control (Cortex region) has its own chemical pool, allowing targeted modulation:
- High dopamine in Cortex → More exploration in planning
- High serotonin in Cortex → Better impulse control in decision-making
- High acetylcholine in Cortex → Better focus in working memory
These regional levels can be accessed via neuromodulator_get_regional with NM_REGION_CORTEX.
Related Documentation
- Memory Layout - Complete memory map and address allocation
- Neuromodulator System - Synthetic neurochemistry layer
- Brain Architecture - Overall system architecture
- Building & Testing - How to build and test the system